Brief Introduction
VLSI - Analyse your chip timing for freeDescription
In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking
Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.
Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more.
I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.
So, hope you enjoy learning this course in the same way we enjoyed making them.
Happy Learning !!
Requirements
- Requirements
- Static Timing analysis - part 1 course needs to be fully completed to start this course. No exceptions
- Knowledge of physical design flow and clock tree synthesis will be helpful
Kunal Ghosh
4 Raiting
VSD - Static Timing Analysis - I
- 4.3
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VLSI - Essential timing checks Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky....
VSD - Static Timing Analysis - II
- 4
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VLSI - Analyse your chip timing for free In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc....
